Interrupt status clear register
| INX_INT | Writing a 1 clears the INX_Int bit in QEIINTSTAT. |
| TIM_INT | Writing a 1 clears the TIN_Int bit in QEIINTSTAT. |
| VELC_INT | Writing a 1 clears the VELC_Int bit in QEIINTSTAT. |
| DIR_INT | Writing a 1 clears the DIR_Int bit in QEIINTSTAT. |
| ERR_INT | Writing a 1 clears the ERR_Int bit in QEIINTSTAT. |
| ENCLK_INT | Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. |
| POS0_INT | Writing a 1 clears the POS0_Int bit in QEIINTSTAT. |
| POS1_INT | Writing a 1 clears the POS1_Int bit in QEIINTSTAT. |
| POS2_INT | Writing a 1 clears the POS2_Int bit in QEIINTSTAT. |
| REV0_INT | Writing a 1 clears the REV0_Int bit in QEIINTSTAT. |
| POS0REV_INT | Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. |
| POS1REV_INT | Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. |
| POS2REV_INT | Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. |
| REV1_INT | Writing a 1 clears the REV1_Int bit in QEIINTSTAT. |
| REV2_INT | Writing a 1 clears the REV2_Int bit in QEIINTSTAT. |
| MAXPOS_INT | Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |